RISC-V Processor Leaderboard
Implementing 5-stage pipelined RISC-V (RV32I) processors in undergraduate computer architecture courses
View GitHub repo by UnaryLab
Metrics
IPC
Instructions Per Cycle
↑ Higher is better
Cycle Count
Total program cycles
↓ Lower is better
Frequency
Synthesis frequency (MHz)
↑ Higher is better
Area
Chip area (mm²)
↓ Lower is better
Power
Power consumption (mW)
↓ Lower is better
Filters